1. Field of Invention
The present invention relates to a transistor and a preparation method thereof, and specifically to a silicon (Si)-germanium (Ge) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof.
2. Description of Related Arts
In recent years, the microelectronic technology centered on silicon integrated circuits develops rapidly. The development of the integrated circuit chip follows Moore's Law, that is, the degree of integration of semiconductor chips doubles every 18 months. In the past, the advancement of the microelectronic technology is based on the continuous optimization of the cost effectiveness of materials and processes. However, with the development of the microelectronic technology, it becomes more and more difficult to reduce the size of a conventional silicon-based Complementary Metal-Oxide-Semiconductor Transistor (CMOS) proportionally. Moreover, most electronic products manufactured using Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have the following problems: First, electric leakage increases as the channel of the MOSFET becomes shorter, and power keeps being consumed even in an off state or standby state. Citing a report from the European Union, IBM points out that 10% of home and office electricity is wasted for the standby state of electronic products. Secondly, restricted by the physical mechanism, a conventional MOSFET has a large sub-threshold swing.
A solution to the above problems is to use a TFET structure. Compared with a conventional MOSFET, the TFET has a different working principle that makes further reduction of the circuit size possible. The TFET has the advantages of a low leakage current, small sub-threshold swing, and low power consumption. However, the ON-state current of the silicon-based TFET is small. Although materials with a narrow band gap (such as Ge and silicon germanium (SiGe)) may improve the ON-state current, these materials increase the OFF-state current.
A SiGe heterojunction TFET increases the ON-state current while maintaining a low OFF-state current. However, the SiGe heterojunction is mainly prepared through an epitaxial technique. For SiGe film with a high Ge content, due to the limit of lattice mismatch (4.2%) between Ge and Si, when the material grows beyond a critical thickness thereof, a lot of defects are incurred, leading to greater electric leakage of devices. The devices also require a certain thickness of the film. If the film is excessively thin, a device process is difficult to implement. Therefore, a feasible method for implementing a high-quality SiGe heterojunction structure and maintaining a certain film thickness is required, so as to produce a high-performance SiGe heterojunction TFET.